Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones and others. One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual devices. Smaller devices can operate at higher speeds since the physical distance between components is smaller. In addition, higher conductivity materials, such as copper, are replacing lower conductivity materials, such as aluminum. One other challenge is to increase the mobility of semiconductor charge carriers such as electrons and holes.
One technique to improve transistor performance is to strain (i.e., distort) the semiconductor crystal lattice near the charge-carrier channel region. Transistors built on strained silicon, for example, have greater charge-carrier mobility than those fabricated using conventional substrates. One technique to strain silicon is to provide a layer of germanium or silicon germanium. A thin layer of silicon may be grown over the germanium-containing layer. Since the germanium crystal lattice is larger than silicon, the germanium-containing layer creates a lattice mismatch stress in adjacent layers. Strained channel transistors may then be formed in the strained silicon layer.
Another technique is to provide a stress layer over the transistor. Variants of stress layers can be used for mobility improvement and performance boost of devices. For example, stress can be provided by a contact etch stop layer (CESL), dual layers, and stress memory transfer layers. Most of these techniques use nitride layers to provide tensile and compressive stresses; however, other materials can be used in other applications, e.g., HDP oxide layers.
Another method for inducing strain involves inducing stress in the STI regions adjacent to the transistor. For example, using an HDP oxide fill within the STI regions would provide compressive stress. Other materials, such as porous oxide, could also be used to impart stress in a device; however, some of these porous materials are not well suited to withstand the rigors and conditions of semiconductor processing.
In the field of small, densely packed applications using small geometry CMOS transistors, however, the use of STI regions to enhance carrier mobility becomes challenging because, as the geometries of the semiconductor process get smaller, higher stress is required within the STI regions in order to maintain adequate performance. What is needed are improved and manufacturable methods and materials to maximize the amount of channel stress.